An overview of achieving energy efficiency in on-chip networks

Due to the increasing bandwidth demand for the network-on-chip (NoC), interconnection networks become a dominant source of energy consumption in systems-on-chip (SoCs) and chip multi processors (CMPs). Therefore, energy efficient NoC is key to a successful SoC development. This paper presents an overview of different techniques to achieve energy efficiency at the different levels of NoC design including: a component level where dynamic voltage scaling (DVS) and dynamic link shutdown (DLS) techniques are reviewed b circuit level, e.g., voltage swinging of signals c architectural level, where specialised tools, such as Wattch and Orion are discussed. We also summarise research on thermal optimisation issues. To the best of our knowledge, this is the first survey of recent research results on the area.